Design And Reuse

Arasan furthers MIPI I3C® compliance with its participation at the I3C® interop in Taipei

Arasan Chip Systems, announces its participation at the MIPI I3C® Interop Session in Taipei with its I3C® Host IP, I3C® Dual IP and I3C® Device IP on Oct 19-20, 2026 ...
Design And Reuse

QuantalRF Samples DPD-Efficient Linear Wi-Fi 7 and Wi-Fi 8 FEM with Up to 3dB More Mask-Compliant Power at 160 and 320 MHz

QuantalRF, the pioneering developer of RF semiconductor and antenna solutions, today announced it has started sampling the QWX27104, a DPD-efficient linear front-end module (FEM) for Wi-Fi 7 and Wi-Fi ...
Design And Reuse

ASML and TSMC Announce Initiative to Pioneer Industry Transition to Large-Format Photomasks for High NA EUV

On September 7, in advance of the SPIE BACUS Conference, ASML and TSMC formed a collaborative industry initiative to drive the transition to 12-inch photomasks, maximizing the value of High NA EUV ...
Design And Reuse

SEMI urges broader Chips Act 2.0 to boost Europe’s chip competitiveness

SEMI is urging European policymakers to use the proposed Chips Act 2.0 to improve the region’s semiconductor competitiveness, strengthen supply chain resilience and encourage investment across the ...
Design And Reuse

BOS Semiconductors CEO Featured in Open Chiplet Atlas Community Voice

BOS Semiconductors is pleased to share that Dr. Jaehong Park, CEO of BOS Semiconductors, was featured in the Community Voice section of the Open Chiplet Atlas® (OCA) newsletter.
Design And Reuse

Arm expands AI infrastructure for the agentic era with AGI CPU and Neoverse CSS N4

Across the broader cloud ecosystem, companies are already supporting agentic AI on Arm. Google Cloud is running agent sandboxes on Axion-based GKE, Microsoft Azure is accelerating sandbox tool ...
Design And Reuse

BOS Semiconductors Joins Arm Total Design for Physical AI

BOS Semiconductors has joined Arm Total Design for Physical AI, a growing ecosystem bringing together more than 80 companies across the technology stack to accelerate the development and deployment of ...
Design And Reuse

Altera Adds Post-Quantum Security to Agilex 3 and Agilex 5 FPGAs

Altera Corporation, the world’s largest pure-play FPGA solutions provider, today announced post-quantum cryptography (PQC) support for Agilex ® 3 and Agilex 5 FPGAs, bringing quantum-resistant ...
Design And Reuse

SoC PLANNER: A New Generation of Automated SoC Design Exploration Managing Cost-Effectiveness and Sustainability

CEA, Defacto Technologies, and Innova Advanced Technologies today announced the completion of SoC PLANNER, a three-years project funded by BPI France, as part of the France 2030 program, and aiming to ...
Design And Reuse

EnSilica to open Space and Communications Semiconductor Centre of Excellence in Milan

The centre initially plans to recruit 20 specialist modem and mmWave engineers over the next six months, expanding EnSilica’s engineering presence in the European Union and enabling closer ...
Design And Reuse

Ceva and LG Electronics Partner to Accelerate UWB Adoption Across Automotive, Industrial and Consumer SoCs

The collaboration pairs Ceva-Waves™ market leading UWB baseband IP and software with UWB radio frequency (RF) technology developed by LG’s SoC Center, giving customers a silicon-ready platform for ...
Design And Reuse

Samsung Electronics and ASML expand strategic collaboration for next-generation semiconductor manufacturing

SEOUL, Korea and VELDHOVEN, the Netherlands -- Samsung Electronics and ASML today announced an expansion of their long-standing strategic partnership, deepening collaboration on High NA EUV ...