Design And Reuse

CAST Introduces 100 Gbps TCP/IP Hardware Stack IP Core for High-Performance ASIC and FPGA Designs

TCPIP-100G joins CAST's broad portfolio of Internet Protocol hardware stacks and networking IP, which includes TCP/IP and UDP/IP stacks from 1G through 400G, Ethernet MACs, MACsec engines ( 1G / 10G ) ...
Design-Reuse

ai& and Tenstorrent Launch JapanFold, Bringing Open-Source, Sovereign Drug Discovery to Japan

ai& and Tenstorrent launched JapanFold, a drug discovery platform running on ai&'s sovereign infrastructure, powered by Tenstorrent Galaxy™ superclusters. ai& and Tenstorrent launched JapanFold, a ...
Design And Reuse

SEMI urges broader Chips Act 2.0 to boost Europe’s chip competitiveness

SEMI is urging European policymakers to use the proposed Chips Act 2.0 to improve the region’s semiconductor competitiveness, strengthen supply chain resilience and encourage investment across the ...
Design And Reuse

QuantalRF Samples DPD-Efficient Linear Wi-Fi 7 and Wi-Fi 8 FEM with Up to 3dB More Mask-Compliant Power at 160 and 320 MHz

QuantalRF, the pioneering developer of RF semiconductor and antenna solutions, today announced it has started sampling the QWX27104, a DPD-efficient linear front-end module (FEM) for Wi-Fi 7 and Wi-Fi ...
Design And Reuse

Altera Adds Post-Quantum Security to Agilex 3 and Agilex 5 FPGAs

Altera Corporation, the world’s largest pure-play FPGA solutions provider, today announced post-quantum cryptography (PQC) support for Agilex ® 3 and Agilex 5 FPGAs, bringing quantum-resistant ...
Design And Reuse

BOS Semiconductors CEO Featured in Open Chiplet Atlas Community Voice

BOS Semiconductors is pleased to share that Dr. Jaehong Park, CEO of BOS Semiconductors, was featured in the Community Voice section of the Open Chiplet Atlas® (OCA) newsletter.
Design And Reuse

Imec scales NbTiN superconducting circuits to 30nm

Imec has demonstrated a three-metal-level superconducting circuit based on niobium-titanium-nitride (NbTiN), reaching a design density of 3.8 million Josephson junctions per cm². The Belgian R&D ...
Design And Reuse

Embedded Security explained: Digital signatures

Typical embedded applications include: Secure boot: Verify firmware before execution. Firmware updates: Accept only ...
Design And Reuse

SerDes, Ethernet and the silicon that connects them: Why SerDes for high-bandwidth sensors?

SerDes (Serializer/Deserializer) fits this profile. It converts wide parallel sensor data into a high-speed serial stream over a clean point-to-point path, minimizing protocol overhead and latency, ...
Design And Reuse

SoC PLANNER: A New Generation of Automated SoC Design Exploration Managing Cost-Effectiveness and Sustainability

CEA, Defacto Technologies, and Innova Advanced Technologies today announced the completion of SoC PLANNER, a three-years project funded by BPI France, as part of the France 2030 program, and aiming to ...
Design And Reuse

BOS Semiconductors Joins Arm Total Design for Physical AI

BOS Semiconductors has joined Arm Total Design for Physical AI, a growing ecosystem bringing together more than 80 companies across the technology stack to accelerate the development and deployment of ...
Design And Reuse

EnSilica to open Space and Communications Semiconductor Centre of Excellence in Milan

The centre initially plans to recruit 20 specialist modem and mmWave engineers over the next six months, expanding EnSilica’s engineering presence in the European Union and enabling closer ...