Design And Reuse

Why analog anti-tamper security IP is crucial in the PQC era

PQC is changing how digital systems defend against potential mathematical attacks. PQC algorithms are designed to protect against hackers who try to recover secret keys by breaking the underlying ...
Design And Reuse

BrainChip AKD1500 Now Available in Compact M.2 Form Factor, Enabling Fanless Edge AI in Industrial and Commercial Designs

The new AKD1500 M.2 module is positioned as a low-cost, ultra-low-power edge AI accelerator available for plug-and-play deployment in the smallest M.2 standard socket, giving hardware designers a drop ...
Design And Reuse

ETSI Raises the Bar for Secure Boot Under the Cyber Resilience Act

One of the more interesting aspects of the ETSI draft is that it treats secure boot as part of a wider chain of trust rather ...
Design And Reuse

How JPEG XS powered all 104 FIFA® World Cup matches

JPEG XS & ST 2110 formed the backbone of the contribution network that made this decentralization possible. While local Venue ...
Design And Reuse

Synopsys and Intel Foundry Fast-Track Customer Readiness from Silicon to Systems on Intel 14A

(Nasdaq: SNPS) today announced at the 2026 DAC Chips to Systems Conference, expanded collaborations with Intel Foundry with the certification of AI-powered EDA flows on Intel 14A process technology, ...
Design And Reuse

Synopsys Advances Agentic AI Chip Design with AMD and Microsoft

Introduces Industry's First Autonomous EDA Workflows on Microsoft Discovery to Accelerate Engineering from Specification to Silicon Synopsys is advancing an open, interoperable agentic AI stack for ...
Design And Reuse

Andes Technology and Mirabilis Design Announce Collaboration on System-Level Models for Andes RISC-V Processor IP

As part of this collaboration, Mirabilis Design has developed and validated system-level models for the Andes AX66 multicore and Andes A45 processors using the VisualSim® platform. The models allow ...
Design And Reuse

IP Cores, Inc. Releases LZR4D Terabit-Class Ultralow-Latency Single-Engine LZ4 Decompressor Core

IP Cores, Inc. ( has announced the release of the LZR4D core, a single-engine ultralow-latency hardware decompressor for the widely used LZ4 lossless compression format. The LZR4D produces 256 bits of ...
Design And Reuse

Silvaco to Accelerate Physics-Based Digital Twins for Semiconductor Design and Manufacturing Using NVIDIA AI and Accelerated Computing

Silvaco Group, Inc. (Nasdaq: SVCO) (“Silvaco”), a leading provider of TCAD, EDA software, and semiconductor IP solutions, and NVIDIA, a global leader in accelerated computing and AI, today announced a ...
Design And Reuse

True Circuits Announces the JSPICE™ Design Environment (JDE™) will be Offered to the JDE Ecosystem Open Source

Following on announcements of JDE availability through a beta program over the last two years, TCI sees the immense value of putting JDE in the hands of the open source analog design community so ...
Design And Reuse

Synopsys Showcases Comprehensive Autonomous Engineering Workflows from Silicon to Systems, Developed with NVIDIA Technology

Demonstrating Synopsys' first fully autonomous computer-aided engineering (CAE) workflow for thermal management and electronic device cooling capable of autonomously executing set-up, pre-processing, ...
Design And Reuse

Siemens advances self-verifying agentic AI workflows for semiconductor and PCB design

Enables agentic AI workflows that help engineers improve productivity and design quality across the electronic design automation (EDA) lifecycle Integrates with Siemens’ Intelligence Center X, ...