Design And Reuse

RaiderChip NPU leads edge LLM benchmarks against GPUs and CPUs in academic research paper

The study, aimed at comparing the real-world behavior of each platform under intensive inference workloads, evaluates CPUs, ...
Design And Reuse

CAST Introduces Microsecond Channel Controller IP Core for Automotive Power and Sensor Interfaces

Woodcliff Lake, New Jersey — Semiconductor intellectual property provider CAST today announced the MSC-CTRL Microsecond Channel Controller IP core, a configurable master controller that gives ASIC and ...
Design And Reuse

BrainChip Announces $25 Million (USD) Funding Ahead of CES to Power Next-Gen Edge AI

BrainChip is expanding its product portfolio to capture more of the global neuromorphic computing market which Grand View Research projects will reach USD 20.27 billion by 2030, growing at a compound ...
Design And Reuse

Arteris to Expand Portfolio with Acquisition of Cycuity, a Leader in Semiconductor Cybersecurity Assurance

Expanding our technology portfolio to include Cycuity’s hardware security assurance products will enable our customers to achieve secure on-chip data movement.” Semiconductor cybersecurity assurance ...
Design And Reuse

Perceptia Announces Availability of Cryogenic 10-bit ADC and DAC IP in GF 22FDX

Sydney, Australia – Perceptia Devices today announced the availability of its new cryogenic 10-bit analog-to-digital ...
Design And Reuse

Silicon Creations and Chip Interfaces Announce Successful Interoperability for JESD204B/C, Interlaken, and CPRI

Silicon Creations, a leading provider of high-performance analog and mixed-signal IP today announced the successful validation of interoperability of Chip Interfaces’ JESD204B, JESD204C, Interlaken, ...
Design-Reuse

Adapting Foundation IP to Exceed 2 nm Power Efficiency in Next-Gen Hyperscale Compute Engines

Competing in the booming data center chip market often comes down to one factor: power efficiency. The less power a CPU, GPU, or AI accelerator requires to produce results, the more processing it can ...
Design And Reuse

India Paves Dual RISC-V Tracks with C-DAC and Startup Silicon

India’s RISC-V ecosystem is gaining strength through two parallel efforts, one led by C-DAC, the other emerging from a new wave of chip startups.
Design And Reuse

Semiconductor industry enters unprecedented ‘giga cycle’, says report — scale of artificial intelligence is rewriting compute, memory, networking, and storage economics ...

A growing body of forecasts from AMD, Nvidia, Broadcom, and major research firms now points toward a semiconductor market that passes the trillion-dollar threshold before the decade closes, driven by ...
Design-Reuse

Beyond the Core: Tackling system-wide debugging for complex SoCs with Tessent UltraSight

The world of System-on-Chips (SoCs) is evolving - with the advancement of generative AI, the increasing demand for high-performance compute, and the innovative shift towards multi-chiplet ...
Design And Reuse

CoMira Announces One of the Industry’s First Commercially Available UALink IP Solutions for Next-Generation AI Scale-Up Networks

The CoMira UALink IP is a configurable, multi-SKU portfolio that delivers full Transaction Layer, Data Link Layer, and Physical Layer implementations of the UALink 200G 1.0 specification. Designed for ...
Design-Reuse

SoftBank's Arm plans to set up chip training facility in South Korea

SEOUL - South Korea's industry ministry and SoftBank's (9984.T), opens new tab chip unit, Arm Holdings, have signed an agreement to strengthen the country's semiconductor and Artificial Intelligence ...