Standalone GPUs are being replaced by heterogeneous SoCs and chiplets that combine CPUs, GPUs, and NPUs to eliminate memory ...

As AI-driven workloads continue to push the boundaries of compute scale, power efficiency, and bandwidth density, conventional die-to-die interconnect technologies—such as SerDes-based links and wide ...

Low-latency fabrics, topology-aware scheduling, and tiered memory bring compute closer to data and reduce coordination ...

PCIe remains a critical technology for non-AI processing. For AI, PCIe will be strengthened by scale-out, agentic AI, and ...

A new architecture enables higher data rates and densities while remaining pin-compatible with traditional DIMM.

Scaling to tens of millions of CPO units per year requires the industry to first settle on automated, cost-effective methods ...

Ayar Labs and Wiwynn A CPO link is in one direction from the driving laser through the optical engine (OE) on the XPU, ...

Reliable performance at higher data rates requires tight coordination between clocking, power delivery, and system-level management.

This post addresses the specific hurdle of effective and efficient manufacturing tests for these complex devices. It outlines ...

We have started to see what may be the largest disturbance in the role of a verification engineer since the founding of the ...

How agents can be used to divide and conquer IC design problems.

Analog behavior is difficult to compress into simple pass/fail decisions that could reduce redundant coverage.