Warpage is shifting from a global bow specification to a process-dependent surface-shape problem that affects bonding, alignment, lithography, reliability, and downstream assembly. Panel-level ...

HW methods to throttle AI; M3D DRAM; interconnect signal-integrity analysis; 3D mask effects in high/hyper-NA EUV litho; ...

This research is significant in that it proposes a new design principle that allows the flow of light within photonic ...

The use of AI agents in chip design has been limited to small portions of the design flow. Engineers have been proceeding cautiously to understand how agents work, how to ensure they are delivering ...

Scaling NoCs across chiplets requires earlier validation of coherency, congestion, thermal effects, and fault behavior.

AI-driven compute demands have led to several distinct supply chain bottlenecks for data centers. Legacy power management ...

Change is coming, but how quickly depends on the availability of data and when chipmakers are confident enough to let AI take over.

Newer nonvolatile memory (NVM) technologies are poised to take over from flash in embedded applications on newer process ...

Photonics is forcing EDA to verify not just chips, but the physics of light inside full electro-optical systems.

As semiconductor devices become increasingly central to automotive, industrial, aerospace, medical, and other safety-critical applications, functional safety has evolved from a specialized engineering ...

Intel’s expansion; Cadence AI super agent for PCB, advanced packaging; photonics fab wars; earlier Yongin fab; German funding; new CHIPS Act award; HBM standard; Quadric funding; AMS acquisition; ...